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The Challenges for the New Semiconductor Packaging Technology Era
Keywords: Semiconductor Packaging, MRAM, R-RAM, P-RAM , TSV
The packaging technologies now can increase the density, performance and convergence of the product more than the fab. processes does in semiconductor area. The cost ownership to increase the density and scale down of the chip jump up more than expected and will be the limiting factor. Even the industry pour a lot of endeavors to develop the new memory such as MRAM, R-RAM, P-RAM and so on, time for developing and getting the stable processes is needed. The efficient way to meet the requirements of the industry now is to combine the same or different chips by using the packaging technologies in one package. The 1st level interconnection method for future package is now changing from wire bonding to flip chip and through silicon via to increase the density and performance of the product. Most of the industry loves the through silicon via technology, but a lot of hurdles to overcome exist and could be solved by collaboration between material, tool supplier, OSAT, foundry and IDM. The supply chain management and core disruptive technologies, especially low cost/high productive bond/diebond, stacking process and thermal management, are crucial elements for TSV to penetrate into the market. Speaker Bio: Dr. Nick (Namseog) Kim is a University major in Material Science & Engineering. He obtained his Ph.D. in the metallurgy at Seoul National University and joined Samsung Electronics from 1996 to 2010.2. After studying mechanical engineering at UC Berkeley, from 2006.5 to 2010.2, he developed and managed the Future Packaging Technology such as Wafer Level Bumping, Redistribution for Stacking, Wafer Level Package, Through Silicon Via Technology and Low Cost & Innovative Packaging Technology etc., at Samsung Electronics. He developed the LED Chip and its Package as a CTO of Central R&D Center at Seoul Semiconductor Corp., from May, 2010 to April, 2011. Nick is currently responsible for the future electronic packaging technologies at Hynix Semiconductor Inc. Outside Activities includes… . ’06 – ‘07: IMAPS ISMP07/08 Prep. Member . ’07 – ‘08: Semicon Korea STS08/09 Chapter Member . ‘07: IMAPS Korea Business Director . ‘08.6 – 2010.2: ITRS A&P (Assembly & Package) Chapter, Korea Representative . ’09.1 – 2010.2: Semicon Korea Electro-package and Interconnect Product Chapter Chairman
Dr. Nick(Namseog) Kim, Vice President, Head of PKG R&D Group 2
Hynix Semiconductor Inc.
Gyeonggi-do, -

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