Abstract Preview

Here is the abstract you requested from the DPC_2012 technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.

Proven Cleaning Technology Solutions for Lead-Free Micro-Bumping Processes
Keywords: Cleaning, Lead-Free, Copper micro-pillars
Opportunities for developing new and enabling packaging schemes are being pursued as part of device improvement strategies for electronic products. Processes such as embedded technologies in wafer level packaging and 3-D chip architecture schemes open up opportunities for realization of a variety of package configurations. As a result, there are many opportunities to impact both device performance and the processes used to create them. In the area of electroplated solder application, one area of growing interest is cleaning technology. There is a need for an integrated process to fabricate defect-free copper pillars with lead-free caps and lead-free solder plated bumps compatible with advanced packaging schemes and with improved yields and reliability. Photoresist removal and surface preparation have been identified as critical to the success. In familiar and widespread technology using 150 micropitch solder bumping, the introduction of RoHS rules for lead-free solder bump compositions, (SnAg, SnAgCu), proceeded in the absence of an integrated and tailored process capable of defect-free surface preparation. It was relatively simple for solder bump compositions in many devices to be converted to lead-free alloys. However, new challenges continue to arise in higher volume fabrication of SnAg micro-pillars (micro-pillars) or copper micro-pillars with lead-free solder caps as the bump pitch approaches 25 microm with aspect ratios of 1:1 or 1.5:1. Individual processes that are involved in the total integration, including (1) dielectric cleaning steps, (2) PVD seed Ti and Cu deposition, (3) electroplating, (4) thick photoresist application and patterning, (5) photoresist removal, (6) associated descum processes, and (7) copper seed metal etch steps, have been challenged to meet the demands. New geometries, higher aspect ratios and very dense solder bump arrays have created further challenges for these processes, stretching the older 150 microm technology beyond its capability. The focus of this paper is to identify a reliable route to defect-free copper micro-pillars with lead-free caps and lead-free solder plated micro-bumps after photoresist removal in applications compatible with advanced packaging schemes and with improved yields and reliability.
Kimberly D. Pollard, Technology Manager
Dynaloy LLC
Indianapolis, IN

  • Amkor
  • ASE
  • Canon
  • EMD Performance Materials
  • Honeywell
  • Indium
  • Kester
  • Kyocera America
  • Master Bond
  • Micro Systems Technologies
  • MRSI
  • Palomar
  • Plexus
  • Promex
  • Qualcomm
  • Quik-Pak
  • Raytheon
  • Specialty Coating Systems