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Modeling of the Punch-Through Effect in Normally-On SiC JFET used in High Temperature Inverter for Aerospace Application
Keywords: Normally-On SiC JFET, Punch-Through Effect, Modeling
There is a new trend in aerospace industry to integrate power electronic converters, i.e. inverters, as close as possible to actuators in order to decrease the total mass of the system. Such converters are located in harsh environment with ambient temperature as high as 225 °C. Therefore, the inverter should be designed to withstand temperature up to 225 °C. Normally-On SiC JFET components made possible such high temperature inverter. In order to predict the behavior of the system, for instance to design EMI filter, it is necessary to model the switching device. Several papers are dealing with the modeling of normally-on SiC JFET components but none of them integrate the behavior of the gate during punch-through effect. Punch-through effect happens when the two below conditions are met, • Depletion layer around the gate meets the depletion layer around the source; • A high reverse voltage, greater than the punch-through voltage, is applied between the gate and the source terminals. The punch-through effect allows hole to cross the gate-to-source potential barrier, and a punch-through current flows in the gate. Punch through effect arises in SiCED/Infineon normally-on JFET because the structure has two gates P+ (one is buried) at two different voltage levels. During switching, the Miller capacitance of the JFET may induce punch-through effect due to high dv/dt. The punch-through effect leads to power dissipation in the gate, which can degrade the gate metallization of the JFET. In order to define the optimal gate-to-source blocking voltage, it is necessary to determine the expression for voltage at which the punch-through current starts flowing in the device. A qualitative description and a detailed one-dimensional analytical expression of the injected current through the barrier height corresponding to the punch through effect in SiC JFET are presented in the first part. Experimental validation of the model is proposed in a second part.
Fabien Dubois, PhD Student
Universite de Lyon, Ampere Laboratory/Hispano Suiza SAFRAN Group
Villeurbanne, Rhone Alpe

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