Here is the abstract you requested from the HiTEC_2012 technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.
|Low Power, Latch-Up Immune High Temperature Digital Components Fabricated with HardSILTM Technology on Bulk Silicon|
|Keywords: HardSIL, latch-up immune, low power|
|High temperature digital electronics for down hole drilling and other industrial applications now require extended lifetimes and reliable operation in environments exceeding 200˚C. Up-screening commercial-off-the-shelf (COTS) digital components, even when coupled with elaborate design, packaging, and other engineering workarounds, is not a viable alternative for most digital components above 200˚C. As a result, dramatic trade-offs in capability are usually endured when electronic modules are pushed from 150-175˚C to 200˚C. Silicon-on-insulator (SOI), once assumed the breakthrough technology to extend reliable high temperature operation for digital electronics, has also not delivered solutions owing to fundamental issues limiting its adoption: 1) very limited availability of design IP for delivering the wide range of digital components required, and 2) very high leakage current at elevated temperatures for high density circuits forcing designers to trade-off power budgets for functionality and capability. When they are used in high temperature applications, SOI components are fabricated with very large (i.e., low density) design rules typically lagging the higher performance, higher density COTS digital parts by five or more generations. We will report our progress on our latch-up immune, low power HardSILTM bulk CMOS technology for high temperature applications. High density CMOS SRAMs have been produced on bulk silicon at both 180nm and 130nm technology nodes at a high volume commercial fab using a modified CMOS process that hardens the junction isolation and has demonstrated latch-up immune and low power performance at high temperatures up to 225˚C. In addition, we will introduce our new 130nm high temperature Metal Programmable System On Chip (MPSOC) platform utilizing the proven HardSILTM technology. This flexible, high density logic fabric and specific design considerations will be discussed in detail.|
|David Duff, Director of Marketing
Silicon Space Technology