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Small Pitch Micro-Bumping and Experimental Investigation for Under Filling 3D Stacking
Keywords: 3D-Stacking, Underfill, Microbumping
3D-IC integration is commonly identified as the most promising ‘More-than-Moore' technology. By 3D-IC Integration it is possible to put more transistors on the same footprint without the need to shrink transistor sizes. Anyway, as for any new technology, there are many challenges and issues that need to be addressed before moving to high volume manufacturing. A key element for 3D-IC integration is the process of stacking the IC components on top of each other. To realize 3D stacking the bump pitches and die-substrate gap are scaled down to as low as possible, this results in increasing assembly complexity and making more evident the limits of standard processes like capillary UF (Under Fill). In view of this increased complexity, alternative under filling process like NUF (No Flow UF) and WAUF (Wafer Applied UF) are investigated as they can offer sensitive improvements in term of processing and device reliability. In this paper we report the recent results coming from the UF screening and 3D stacking activities. These activities are performed at Imec in the frame of the 3D Imec Industrial Affiliation Program (3D-IIAP). After an introduction on the processing to achieve Cu and CuSn bumps with pitches of 40m (in peripheral array configuration) and 50m (in full area array configuration), we finally present the electrical characterization of the 3D stacks. This characterization is done by measuring the electrical resistance of the daisy chains connections between top/bottom dies bumps. The stacks are done with thermo-compression bonding and using die-to-die approach. The stacks are lately exposed to thermo-cycling processing followed by further characterization.
Antonio La Manna,
IMEC-Belgium
Leuven, Flandre
Belgium


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