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Full Integration and Electrical Characterization of 3D Silicon Interposer Demonstrator incorporating high density TSVs and interconnects
Keywords: Silicon Interposer , high density TSV interconnect, Electrical characterization
Silicon interposers with TSVs appear to open new possibilities thanks to high wiring density interconnections and improved electrical performances given by shorter interconnections from die to die and also from die to substrate. Silicon interposers are also promising in terms of high reliability interconnections for large chips due to minimized CTE mismatch compared to standard organic substrates. A silicon interposer including high density TSVs has been successfully processed and fully tested. Process integration has been characterized, electrical results have been analysed and they will be discussed in this paper. The first part of this paper will focus on integration including several technical challenges such as : 10:1 Aspect Ratio dense TSV of 10m diameter, 2 damascene metal layers with minimum critical dimension of 0.5m, 100,000 25m diameter micro-bumps per die, and 1,500 backside 70m high copper pillars per die landing on a specific backside redistribution layer. The 2 damascene layers have been adapted in order to achieve lower resistivity with high density: the line is 1.4m thick and has a minimum line width and space CD of 0.5m/0.5m. The 10m diameter, 100m height copper filled TSV showing aggressive 50m pitch compared to previous realization has been also fully characterized. The second part of this paper will focus on the electrical data from DC tests achieved after full realization of the silicon interposer. These results show very high yield and a good agreement between measurements and estimated values especially concerning TSV Kelvin and the 1,000 TSVs chain test patterns with respectively resistance values below 25m and 70 m (chain global resistance /1,000). The last part of the paper will present the first results from the RF evaluation (S21 and S11) of the front side rerouting level as well as pattern including TSVs.
Ken Miyairi,
Nagano, Nagano

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