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ACCURATE PREDICTION OF THERMAL RESISTANCE OF FET BY DETAILED MODELING OF HEAT GENERATION AND BACKEND STACKUP
Keywords: thermal modeling, backend stackup, thermal resistance
In typical thermal modeling of a FET structure, the power could be modeled as the heat generation, which is averaged under the entire gate length (gate averaged). However, it is found from the electrical potential field within the channel that the heat generation is actually distributed all the way from source to drain with a heavy concentration around the gate edge at the source side. In a typical case, the peak of the heat distribution is almost four times of the gate averaged. Therefore, accurate modeling of the heat generation averaging over a much smaller region near the gate edge (edge averaged) makes a significant difference. This paper focuses on the comparison of the edge averaged versus the gate averaged modeling development. Furthermore, the detailed topology of the backend stackup layers and their relative impacts on heat dissipation paths are evaluated and the practical simplification is proposed in the modeling development. The result shows that, for a single gate FET die, the thermal resistance is found to be 19% more than that of the gate averaged approach. For a multiple gate FET die, both methods give the same surface temperature on the top surface layer. However, the temperature difference (Tjs) between the junction and the top surface is different between the two methods and the edge averaged approach prediction doubles that of the gate averaged approach. It's also found that Tjs is independent of number of gates and only depends on the backend stackup details between source and drain. The modeling data correlates well with the IR thermal measurement data.
Qun Wan, Staff Packaging Engineer
RF Micro Devices
Greensboro, NC
USA


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