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Design and Process Optimization of Through Silicon Via Interposer for 3D-IC Integration
Keywords: Through Silicon Via (TSV), Chemical mehcanical Polishing (CMP), Deep Reactive Ion Etching (DRIE)
The 3D-IC stacking technology provides improved performance, reduced form factor, and lower cost for applications such as logic-memory integration, image sensors, MEMS, and LED. Invensas corp. is pursuing unique enabling solutions to address many of the more difficult 3D-IC fabrication challenges. We present design and fabrication methods to implement Through Silicon Via (TSV) interposer. The design includes definition of materials, their respective thicknesses and tolerances, and geometries to achieve the specifications. The interposer fabrication includes main modules performed on topside and backside of wafer. These modules include Redistribution Layer (RDL), TSV etch, TSV fill, Chemical Mechanical Polishing (CMP), pad finish, temporary bonding, thinning, via reveal, passivation, wiring, bumping and de-bonding. This technology is deveoped using 200mm and 300mm foundry equipment including Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Deep Reactive Ion Etching (DRIE), electroplating, grinding, CMP, temporary bonding and de-bonding. Efforts on optimizing the profile and sidewall roughness through DRIE parameters and cleaning is discussed and a review of interaction of TSV etch step with next steps will be given. Thermal slide and room temperature slide will be discussed for temporary bonding and de-bonding. The effect of different processes on the final TSV parameters will be reviewed. A discussion on optimization of processes and correlation among the whole will be given. We will present electrical and mechanical characterization and also the process related defects. Finally a summary of TSV fabrication issues, solutions, microbump assembly, and reliability will be presented.
Pejman Monajemi,
Invensas Corp.
San Jose, CA

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