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Process Challenges in 0-Level Packaging using 100m-Thin Chip Capping with TSV
Keywords: 0-level packaging, chip capping, TSV
Zero-level packaging creates an on-wafer, device-scale enclosure around (or sealed cavity for) the MEMS, serving as a first protective interface. This paper presents all the challenges in the fabrication process of zero-level packaging for MEMS implementing "chip-capping" using metal-to-metal bonding. Two features in particular make the package very attractive: (1) Through-silicon via' (TSVs) are implemented in the 100microm thick Si capping chip; the use of TSVs leads to a small(er) footprint and makes the package ready for 3D implementation. And, (2) a metal bond and seal is implemented; metals are the preferred materials to be used for the bond as these provide the best seals, with a low permeation rate for gases and moisture. The 100m thin cap in this process does not have only the capping function but it also has other device integrated on top such as RF structures and sensors. After the processing of the device structures (stress sensor, coplanar waveguides (CPWs)) on the frontside of the cap wafer, the wafer is thinned down to a thickness of 100m thereby using a Si handle wafer. A TSV process is applied from the backside of the cap wafer ("via last approach"). In this paper we focus only in the most challenging steps in fabricating the thin chip capping with TSV such as thinning process, TSV formation and metal interconnects. Another challenging is the metallization of sealing ring and interconnect bump. Both structures are formed at the same time using electroplating. The sealing ring for bond package often has a rather large dimension compared to the micro bump (to bring the contact from bottom MEMS wafer to the top of cap wafer via TSV). This will result in the height differences between sealing ring and micro bump after plating, thus causing an issue later when the cap is bonded with MEMS wafer. The package is hermetic bonded while the micro bumps are not connected. A process solution to planarize metal sealing ring and microbump has been proposed. In conclusion, challenges in processing of the thin Si chip capping with TSV for hermetic 0-level packaging is presented and the solution to overcome the challenges will be discussed in details.
Nga P. Pham, Researcher
Leuven, Vlaam Brabant

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