Here is the abstract you requested from the IMAPS_2012 technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.
|Fine Pitch Copper Interconnects for Next Generation Package-on-Package (PoP)|
|Keywords: Package-on-Package (PoP), Applications processor + memory, Wide I/O|
|Package-on-Package (PoP) is enabling multi-channel memory bandwidth for new multi-core applications processors for today's feature rich mobile computing products. Through-Silicon-Via (TSV) technology is expected to be the ultimate high bandwidth solution for new generations of multi-core mobile processors but still must overcome challenges in process, infrastructure and cost. Existing PoP interconnect solutions featuring conventional solder-balls and solder filled laser vias in the mold cap have insufficient interconnect aspect ratio for fine pitch. PCB interposers are cumbersome and costly. In this paper, a new fine pitch PoP interconnect technology will be presented that is cost effective and achieves high aspect ratio and interconnect density while utilizing commonly used materials and assembly processes. The evaluation test vehicle features a 14mm x 14mm molded bottom package body size with >400 interconnections spanning from the substrate to the top of the mold cap. The 50�m diameter solid copper connections with >6:1 aspect ratio are distributed in 2 peripheral rows at 240�m pitch and are partially embedded within the mold cap. The exposure of the interconnects above the mold cap permits high stacking yields using the smaller BGA solder ball diameters of the top package and effectively achieves a thinner PoP profile. The initial reliability testing indicates a robust PoP solution surviving >1000 temperature cycles and 150 mechanical drops. We will show test vehicle package designs for both top and bottom packages and PoP interconnect layout. The interconnect formation process will be described including the evolution of process parameters, materials and tooling modifications required for integration with today's packaging assembly equipment. Methodology for interconnect exposure above the mold cap and characterization of top-to-bottom stacking processing will be presented along with the reliability performance results including board and package level temperature cycle testing, high temperature storage, autoclave and drop testing.|
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