Abstract Preview

Here is the abstract you requested from the IMAPS_2012 technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.

Electrostatic Discharge Protection and Automated Charge Extraction in High-Voltage Devices and Load Boards
Keywords: Electrostatic Discharge Protection (ESD), High-voltage Devices, Silicon Controlled Rectifiers (SCRs)
This paper presents a novel protection circuit for Electrostatic Discharge (ESD) in high-voltage devices using Silicon Controlled Rectifiers (SCRs) and determination of automated charge extraction path in load boards. ESD has become one of the most critical reliability issues in integrated circuits (ICs). There have been extensive research efforts seeking to improve ESD protection capabilities; the goal is to achieve highly reliable IC products in the presence of ESD threats [1, 2]. As system integration is inching towards "More than Moore" concept, one of the first areas to benefit from them is power management. The combination of computational power, programmability and high power driver circuits provide a platform to control and manage power [3]. The widely accepted solution to high voltage tolerance for deep submicron is the development of Laterally Diffused Metal Oxide Semiconductor (LDMOS) transistors. High-Voltage Laterally-Diffused MOSs (HV-LDMOSs) is extensively used for high voltage applications due to its advantages over other metal oxide semiconductor structures. In high-voltage devices ESD protection is generally provided to the drain connection. We propose to implement SCRs as the ESD protection circuit for the drain connection in HV-LDMOSs. However, the major bottleneck during production testing of high-voltage devices is that once the high voltages are applied then the ESD protection circuit would protect the drain connection but then this high voltage is still present in the load boards which act as an interface between the automatic test equipment (ATE) and the high-voltage device under test (DUT) for an extended period of time even after the applied voltage is removed. Hence charge extraction from the device to the DIB and then to ground has to be done in a time efficient manner to ensure protection. We propose to develop ESD stress models using conventional techniques such as human body model, machine model and charged device model for the high-voltage devices and implement SCRs as protection circuit in the high-voltage DIBs. ATLAS device simulation is done to obtain the ESD stress data of the device which is translated to the protection circuit using a software tool developed to automate high-voltage device testing. The software tool uses the extracted ESD stress model data and the schematic design of the DIB to automatically generate the charge extraction path. The ESD protection circuit additionally designed to the DIBs is triggered on using a unique triggering mechanism. This will be incorporated in the software tool as an additional module and the designed ESD protection circuit will be activated during high-voltage device testing. The ESD protection and automated charge extraction in high-voltage devices and load boards will ensure the safety of the DUT as well as the person handling the test equipment.
Sukeshwar Kannan, Graduate Research Assistant
The University of Alabama, Tuscaloosa
Tuscaloosa, AL

  • Amkor
  • ASE
  • Canon
  • EMD Performance Materials
  • Honeywell
  • Indium
  • Kester
  • Kyocera America
  • Master Bond
  • Micro Systems Technologies
  • MRSI
  • Palomar
  • Plexus
  • Promex
  • Qualcomm
  • Quik-Pak
  • Raytheon
  • Specialty Coating Systems