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Challenges in 3D Inspection of Microbumps Used in 3D Packaging
Keywords: microbumps, 3DIC, inspection
3D devices are the next big thing in the semiconductor world. As more and more functionality is required in a smaller and smaller footprint, going vertical is becoming the only relatively short term solution. Many device manufacturers are devoting capital to develop their own processes, and some are already shipping devices such as FPGA (Field Programmable Gate Array) on interposers. More often, 3D packages require hundreds of thousands of I/O per die. Micro bumps and small pillar bumps are the main bump geometries used in 3D packages as their small pitch and size allow the required number of I/Os. Inspecting these bumps throughout the process is critical as failure after chip to chip or chip to wafer bonding is very costly. Different methods have been used to inspect these bumps over the last few years. The purpose of this paper is to examine challenges in inspection of micro bumps and share the results obtained using laser triangulation, one of the most successful methods.
Reza Asgari, Product Manager
Rudolph Technologies, Inc.
Bloomington, MN
USA


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