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Propagation Delay Analysis in 3D Stacked Memory using Novel MOS Depletion Layer Modeling Approach for TSV
Keywords: 3D Stacked Memory, Through Silicon Via Modeling, Propagation Delay
Rapidly growing complexity in 3D ICs has led an increase in popularity of test methodologies based on delay testing. In this paper, we analyze the physical level design of 3-D stacked memory ICs with Through Silicon Via (TSV) to compute the propagation delay. 3D IC technology has enabled the semiconductor industry and academia to continue with Moore's law. In present day, there is tremendous demand for high density memory ICs with large storage capacity and smaller size [1]. To keep in pace with this growing consumer demand in memory with high level of integration 3D memory ICs were developed by stacking memory modules and logic dies with TSVs. 3D stacking of memory is known to reduce the cost of memory and keep up with the cost reduction approach. TSV technology is proposed as a valuable solution to realize 3D ICs. 3D ICs offer the following advantages " (1) low interconnect latency, (2) higher bandwidth, (3) low power consumption and (4) heterogeneous design. A major bottleneck in incorporating TSVs for 3D ICs is TSV modeling. TSV has additional complex parasitics, process based variations, and structure based reliability issues, thus warranting detailed modelling and analysis. Many analytical and empirical modelling has been reported in the literature [2-4]. This paper discusses the effect of the MOS structure on the overall TSV performance. Towards this, the earlier reported models were modified to include the effect of variable wafer doping profiles. With appropriate choice of parameters, this gives the designer a model with minimum errors and in addition, provides the yardstick for optimum TSV pitch. Further, this provides an interesting option of frequency selective TSV structures, as this model involves a variable capacitor element depending on signal frequency and strength. This paper also applies the model towards optimisation of memory array size in stacking; the key factor being that the TSV delay, for a given process node and TSV pitch, should not contribute to the overall stacked memory arrays' performance. This analysis would help to choose optimium memory array size while stacking, without degradation in overall memory performance. This approach is applicable even for the extreme granulation of single cell stacking. At first level of routing, this optimisation can be effectively used in arriving at first cut memory array size. This approach/analysis can be effectively used as a primary guideline during memory partitioning for stack designs and layout for optimum bandwidth. References: [1]. E. Korczynski, "TSV Integration Differentiations," SEMICON West, 2011. [2]. C. Ryu, J. Lee, H. Lee, K. Lee, T. Oh, and J. Kim, "High Frequency Electrical Model of Through Wafer Via for 3-D Stacked Chip Packaging", Proceedings of 1st Electronics Systemintegration Technology Conference, pp. 215-220, 2006. [3]. S. Kannan, S.S. Evana, A. Gupta, B. Kim and L. Li, "3D copper based TSV for 60GHz Applications," Proceedings of the 61st Electronic Components and Technology Conference, pp. 1168-1175, 2011. [4]. T. Bandhopadhyay, K.J. Han, D. Chung, R. Chatterjee, M. Swaminathan and R. Tummala, "Rigorous electrical modeling of TSV with MOS Capacitance Effects," IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 1, iss. 6, pp. 893-903, 2011.
Kaushal Kannan, Student
Nitte Meenakshi Institute of Technology
Bangalore, Karnataka

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