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GHz High Frequency TSV for 2.5D IC Packaging
Keywords: 2.5D IC Package, Si interposer, TSV
TSV is the key enabling technology for 2.5D & 3D IC stacking solution in FCBGA (Flip Chip Ball Grid Array). As the 2.5D interposer design pushing toward smaller & shorter via due to I/O density and electrical performance, the warpage of thinner interposer is therefore much more challenging in thin wafer handling and assembly process. From the structure point of view, the Si interposer is an additive layer between top side chip(s) and substrate, it is therefore an additional electrical interconnection for the signal between top chip(s) and substrate. As the 2.5D interposer design pushing toward high electrical performance, the reduction of the TSV loss in Si interposer becomes critical, especially for beyond GHz application. This paper presents a TSV structure which demonstrates an interposer prototype covering features such as low temperature fabrication process with low warpage, and minimized TSV parasitic parameters. Real measurement is conducted to validate the electrical performance of TSV interconnection up to 50GHz, and the equivalent circuit model of TSV is proposed, and compared with the measured data. The measurement of this TSV structure has demonstrated the advantages with low parasitics and low insertion loss at high frequency. Full validated reliability test is also presented to verify interposer fabrication, assembly process optimization, and interconnection stability of the 2.5D IC package.
Meng-Jen Wang,
Advanced Semiconductor Engineering (ASE), Inc.
Kaohsiung, TAIWAN

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