Here is the abstract you requested from the IMAPS_2012 technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.
|Design, Optimization and Robustness of Quilt Packaging Superconnect|
|Keywords: Quilt Packaging, Interconnect, Reliability|
|Quilt Packaging (QP) is a novel high speed superconnect (i.e. direct interchip interconnect), developed to improve electrical performance"” signal delay, power loss, etc. In this technique, two or more chips of similar or dissimilar materials are connected along their edges by using metal nodules that protrude out from the edges of chips to effect a direct, chip-to-chip electrical interconnect. High data throughput has already been established for the superconnect, but because of its unique structure, it requires thermal reliability issues to be studied. To this end, simulation models have been developed to study and optimize the robustness of QP. The structure of QP has been fabricated, and thermal cycling tests of several temperature excursions of some standards have been performed focusing on the reliability for various shapes of nodules, the basic physical interconnect unit of QP. The results, both simulated and experimental, assist in designing robust partially-embedded structures. Several simulation models have been developed for the QP system to closely match physical QP structures. Simulations were performed to determine stress over a range of temperatures. Based on thermal stress on nodules embedded in various semiconductors, the material properties of epoxy used to attach substrates to a package, and the optimized shape of nodules have been determined. The fabrication steps include nodule etch, oxide deposition, sputtering seed layer, electroplating, CMP, metal evaporation, separation etch, backside grinding, alignment and soldering chips and finally attaching chips to a package. Thermal cycling tests, following JESD22-A104D and IPC-9701A: TC4, have been performed on the fabricated chips to support the simulation results. The thermal stress results indicated that QP provides a robust structure, in agreement with the simulation results.|
|M. Ashraf Khan, Graduate student
Department of Electrical Engineering, University of Notre Dame
Notre Dame, IN