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Underfill Dispensing for 3D Die Stacking with Through Silicon Vias
Keywords: TSV, Underfill, 3D Die Stacking
In this paper, a 3D stacked package was developed to enable size reduction of miniaturized electronic devices. The developed package was a stacked flip-chip-on-chip structure and eight flip chips were arranged in four vertical levels by using four silicon chip carriers with through silicon vias (TSVs). In each level, 100um solder bumps of flip chips were fanned-in on the silicon chip carrier to form a 7x7 area array with 300um solder bumps, and multiple 100um/300um TSVs were fabricated in each silicon chip carrier for signal interconnection or underfill process respectively. The whole 3D stacked module was stacked layer by layer and then assembled to the printed circuit board by the standard surface mount reflow process. In the underfill process, we used conventional suspending I-Pass underfill with pre-bent needle tip to fill up the gaps of the bottom two chip carriers as it has relatively fast spreading speed. For the top two chip carriers, through-holes underfill with multiple TSVs was used to fill up the gaps downward layer by layer. Unlike the conventional underfill, the encapsulant would not spread into the gaps by the capillary effect unless the dispensed dots obtained enough kinetic energy to break the surface tension at the end of through-holes, and thus low dispensing height or jet valve was needed in through-holes underfill. Finally, both nondestructive evaluations and cross-section inspections were performed to verify the effect of underfill. The 3D X-ray/SAM and cross-section results showed that the combined I-Pass/through-holes underfill gave void-free encapsulation and perfect fillets for the 3D stacked package.
Fred Fuliang Le, PhD Candidate
HKUST
Kowloon, HKSAR
Hong Kong


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