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Electrical Performance of Through-Silicon Vias (TSVs) for High-Frequency 3D IC Integration Applications
Keywords: TSV, modeling, design guideline
TSV is the heart and most important key enabling technology of 3D IC integration. It provides the opportunity for the shortest chip-to-chip interconnects and smallest pad size and pitch of interconnects. Comparing to other interconnection technologies such as the wire bonding, the advantages of TSV are: better electrical performance; lower power consumption; wider data width and thus bandwidth; higher density; smaller form factor; lighter weight; and hopefully lower cost. In this investigation, we propose a set of empirical equations for the electrical performance of a TSV in terms of all the important parameters such as TSV diameter, TSV depth, silicon-oxide thickness, pad-diameter, and TSV pitch has been provided and examined. Emphasis is placed on the determination (based on the present proposed circuit models) of the high-speed signal performance of the TSV with a wide-range of dimensions and parameters. For examples; the TSV diameter is ranging from 5 to 50m, TSV depth is ranging from 50 to 150m, TSV pitch is ranging from 15 to 200m, silicon oxide thickness is ranging from 0.5 to 1m, and pad size is ranging from 10 to 60m. Results from the empirical equations are compared with those based on the detailed 3D finite-element EM-simulation up to 20GHz. It is found that for most key performance parameters, the result difference between the present empirical equations and the 3D FEM-simulation is very small. Also, when comparing with well-known published results, the present empirical equations cover much wider range of dimensions and parameters. Furthermore, the results presented herein are very easy to use. Finally, based on the present circuit models and empirical equations, a set of useful wide bandwidth electrical design guidelines of TSV is provided.
Jui-Feng Hung,
Industrial Technology Research Institute
Chutung, Hsinchu
Taiwan (R.O.C.)

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