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Thermal Stress and Creep Strain Analyses of a 3D IC Integration SiP with Passive Interposer for Network System Application
Keywords: 3D Integration, TSV, Interposer
In this study, the nonlinear thermal stress distributions at the Cu-low-k pads of Moore's law chips and creep strain energy density per cycle at the micro solder joints of a 3D IC integration system-in-package (SiP) are investigated. At the same time, the warpage of the TSV interposer and reliability assessment of micro solder joints in the architecture is examined. The analyzed structure comprises one PCB, one BT substrate, one interposer with through silicon vias (TSVs), two DRAM chips and one high power CPU chip. The high power chip and DRAM chips are supported, respectively on the top-side and bottom-side of the interposer which is 150μm thick. This is not a 2.5D but a real 3D IC integration with a TSV passive interposer. The Moore's law chips are with microbumps and the interposer is with UBMs. The micro gap between chips and interposer is filled with a special underfill. Simulation results show that the corner Cu-low-k pads are subjected to the maximum stresses. Fortunately, because the thermal expansion mismatch between the Moore's law chips and the Cu-filled TSV interposer is not larger, thus the magnitude of maximum stresses is small. Compounding with the help of a special underfill, the stresses acting at the Cu-low-k pad are too small to damage the structure. With the same reasons, the creep strain energy density per temperature cycle (after 5 temperature cycles) at the corner micro solder joints between the Moore's law chips and interposer is small and thus the micro solder joint is reliable for use under most operating conditions. Since the coefficient of thermal expansion of BT-substrate and PCB is larger than that of silicon chips and Cu-filled TSV interposer, it is found that the warpage of interposer is smaller than that of the BT-substrate and PCB. Based on the present results, a set of useful design guidelines of 3D IC integration SiP structure with a passive interposer supporting chips on its both sides and subjected to temperature environmental conditions has been provided.
John H Lau, ITRI Fellow
ITRI
Chutung, Hsinchu, Taiwan
ROC


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