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Large Size Silicon Interposer and 3D IC Integration for System-in-Packaging (SiP)
Keywords: Interposer, TSV, 3D IC integration
The feasibility study of a 3D IC integration SiP has been demonstrated in this investigation. The heart of this SiP is a TSV (through-silicon via) passive interposer (28mm x 28mm) with 2-RDL (redistribution layer) on its top-side and 1-RDL on its bottom-side. This interposer is used to support a very large CPU chip (22mm x 18mm) on its top-side and 2 DRAMs (10mm x 10mm) at its bottom-side (a truly 3D IC integration). The bottom side of this interposer is attached to an organic substrate (40mm x 40mm) (with ordinary lead-free solder bumps), which is lead-free solder-balled on a PCB (printed circuit board). The lead-free micro solder bumps (Cu/Sn) on all the Moore's law chips are made by wafer bumping with a UBM (under bump metallurgy) of Ti/Cu and the bump structure of Cu and Sn. The interposer has been fabricated from a 12" (300mm) wafer. The TSV diameter is 25μm and the thickness is 150μm. The processes for making the interposer module and assembly are: via formation by deep reactive ion etch (DRIE); dielectric layer deposition by PECVD (plasma enhanced chemical vapor deposition); barrier and seed layer deposition by physical vapor deposition (PVD); Cu plating to fill the vias; chemical and mechanical polishing (CMP) of Cu plating residues (overburden); front-side metallization and UBM; TSV revealing; back-side metallization and UBM; ordinary solder bumps mounting; chips to interposer bonding; interposer module to organic substrate attachment; and organic substrate to PCB assembly. The challenges such as the microbumping, thin-wafer handling, TSV revealing; interposer module assembly, and the final assembly the 3D IC SiP and the ways to overcome them will be reported and discussed. Some measurement results of the interposer, interposer with the Moore's law chips, and the final assembly are also presented.
John H. Lau, ITRI Fellow
ITRI
Chutung, Hsinchu,, Taiwan
ROC


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