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Process integration solution for damage-free bevel for deep Si etch applications
Keywords: Damage free bevel, Deep Si etching, microfluidics
This paper reports on the process integration solutions to protect bevel during deep reactive ion etching process. In RIE etching tools with no physical protection, the etching species attack the exposed bevel of the wafer. The damage to the bevel leads to yield loss and numerous processing issues. In this paper we present two generic approaches that can be applied to integration flow requiring deep Si etch up to 230 m deep. We demonstrate these two approaches for silicon lab-on chip (LOC) fabrication. Silicon fabrication technologies allow very accurate, repeatable and reliable system development in bio-medical applications. For LOC, sometimes very deep Si etch up to 250-300 m deep trenches are needed. If the bevel of the wafer is not protected sufficiently in IRE tools, the etching species causes damage to the bevel and edge of the wafer during long etch. This can lead to wafer lost due to very fragile wafer edge and in extreme cases damage to tools in further processing due to all the particles that are generated at the bevel. In this paper we report on two methods to overcome this problem. In the first approach, a thick thermal oxide is grown and then oxide CMP is done to reduce the thickness of the oxide on the surface. The edge and bevel of the wafer has thicker oxide. This oxide is not completely removed from the bevel during oxide hard mask (HM) pattern definition. This allows to etch Si to a depth of 230m. The process is then used to deliver a LOC containing the microreactor where DNA amplification is performed. The second approach is used to deliver a LOC containing micro-pillar filter that is used for DNA separation. For the development of this chip, two different Si etches are required: one for fine structures of 2m and one for the coarse structures of hundreds of microns. In this approach, initially the oxide HM is defined for fine structure, followed by nitride deposition and nitride etch only in the bevel region of the wafer. This allows for the thermal oxide growth only in the bevel region thus protecting the bevel during Si etching. In the next step, coarse structures are etched in Si and thermal oxide is grown in the etched coarse structure. After etching the fine filter structures the remaining oxide is removed. The final processing steps to achieve the final LOC are: bonding to pyrex, backside litho, etch and strip. In this paper we report on two generic integration solutions that can be applied to prevent damage to the bevel of the wafer in both dry and wet Si etch approaches. These methods are demonstrated on two different process integration schemes to develop a LOC used in biomedical applications.
Bivragh Majeed, Researcher
Leuven, Belgium

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