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Simulation and Experiment of Molded Underfill Voids
Keywords: void, BGA, MUF
The molded underfill (MUF) has become one of the trends in the IC packaging industry due to its simplification of assembly process step and the saving of the cost. However, for the fine pitch flip chip bumping array, the void generation is one serious issue causing the short of the electrical connections and the cracking of the bumps. In this paper, the main focus is to predict the void generation and to compare with the experimental data. The correlation data function as the baseline for design engineers to design various bumping patterns. The early stage “numerical” experiment not only can predict the risk of voids but also provide the best economic approach without the need to spend trial and error budget. A 4 segments mold strip, with totally 64 packages populated on it, is used in the experiment. The process parameters are programmed and recorded for later comparison. The filling, packing, and curing of molding compound are carefully chosen in order to see their effects. After the assembly process, each package is scanned with C-SAM to check if the voids appear. For FEM numerical simulation, only one segment of the substrate strip, with totally 16 packages, is modeled to save computational resources and time. However, all the bumps, on each of the package, are modeled in order to check how the flow field is affected by the packages. Furthermore, the voiding possibilities are studied with a numerical scheme. In conclusion, we have obtained good match of experimental data vs. simulation data. The prediction of voiding location is very close to each other. A series of mold compound flow behaviors and process parameters are also studied to provide various options of packaging designs.
MyoungSu Chae, engineer
StatsChipPAC
fremont, ca
USA


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