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|Thermomechanical Design for Fine Pitch 3D-IC Packages|
|Keywords: thermomechanical design, fine pitch, 3d-ic|
|Three dimensionally (3D) integrated devices with fine-pitch interconnections and through silicon vias (TSVs) are one of the most promising vehicles for continuous computer performance growth. In 3D modules with organic interposers, challenges still remain in reducing the failures caused by chip package interaction (CPI). In large die 2D modules, high filler loading underfill materials with a high modulus and a low coefficient of thermal expansion (CTE) are thought to be mandatory in reducing the stress of the solder interconnections between the Si die and the laminate. Uncured underfill materials with high filler loading generally show high viscosity. However, in fine-pitch 3D modules, the use of high viscous materials can degrade the process ability, since the gaps between silicon dies are narrow. In this study, with the aim of improving the process ability for 3D device fabrication, we show that one can expand the selection range of mechanical properties of interchip underfill materials by stress reduction of 3D modules through structural parameter optimization. The stress analysis of the 3D modules showed that, in certain range of structural parameters, the stresses on the die stack modules become low even for the modules with the interchip underfill materials with low Young’s modulus and high CTE. We performed thermal cycle tests of two-die stack organic packages with thermomechanically stress-reduced structure with several kinds of underfill materials having different filler loading. The 3D modules with the interchip underfill layers with low Young’s modulus and high CTE as well as those with high Young’s modulus and low CTE passed the thermal stress test of 1000 cycles. Our study shows that we can expand the selection range the interchip underfill material properties through optimization of thermomechanical 3D module design. We can improve the process ability of the 3D module assembly by balancing the stress in the global stacked structure and the local stress on the interconnections. Our results showed that even the low modulus/high CTE underfill materials, such as lower filler loading epoxy resins could become one of the options for interchip underfill layers. This work was entrusted by NEDO Development of Functionally Innovative 3D-Integrated Circuit (Dream Chip) Technology Project that is based on the Japanese government's METI “T Innovation Program.|