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Stacked Chip Thermal Model Validation using Thermal Test Chips
Keywords: thermal test chip, stacked chips, thermal management of semiconductors
Increasing demands on density, functionality and performance in small package footprints has lead to a higher market share for stacked-chip packaging. This trend has brought with it the need for better un-derstanding of thermal issues associated with getting the heat out of the various chips in the stack. Typically, thermal simulation models are used to gain an insight to heat flow issues in complex multi-chip packages. The validity of the models and the assumptions drawn from the model results are ques-tionable unless measurements are used to validate the model results. Unfortunately, validation measurements are difficult to make on multiple-interconnected chips and, even if they can be made, often do not provide sufficient certainty and detail to accurately validate the model. For example, using the substrate isolation diode in an application chip will provide a junction temperature measurement. But that measurement is instead a weighted average of the temperatures across the chip and does not provide for any spatial resolution relative to the highest temperatures on the chip. This is of particular concern on large square chips and chips with a high X-Y aspect ratio. Thus, attempting to use measurement data in this case to validate a thermal model leads to less than ideal results. A similar issue with the application chip approach is determining the specific location, area and magnitude of the heater power (hot spot). To address the problems with measurement of temperature in multi-chip packages a thermal test chip (TTC) has been developed and tested. The TTC is specifically designed to provide known locations for both temperature measurement and heat flux generation. Use of the TTC provides known power in specific spatial locations, thus making the model generation and validation easier and more accurate. Once there is greater confidence in the model, the model can be varied to study heat flow and junction temperature under a variety of packaging approaches and environmental conditions.
Thomas Tarter, President
Package Science Services LLC
Santa Clara, ca
USA


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