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Managing Voids in Underfill Process within 5-micron Gap Under Large Die
Keywords: Underfill, Voids, Large Die
In today's microelectronic packaging, components are being designed smaller and smaller, and then assembled denser and denser to fit more functions into compact portable devices. To enable this shrinking size, more manufacturers are using flip chips that have more I/O and smaller bump sizes. In a recent study, the author reviewed a technique to underfill a flip chip with a 5-micron gap and complex features under 3cm^2 InP die, and to optimize the process to achieve void-free underfill. Aided by a cutting-edge modern dispenser, nanoliter dots were jetted from above the die to form a thin line beside the die edge, and multiple thin lines were used in certain sequence to fill the gap. All parts underfilled by this line-dispense were investigated to be voids-free after cure. No substrate surface treatment was needed. For dot-dispense, substrate surface treatment and more careful design of dispense sequence helped reducing voids. This study was compared to a manual dot-dispense technique used by the customer that was unable to meet specifications of unit per hour, accuracy, repeatability and void-free. The achievement of void-free automated underfill into a 5-micron gap with complex features underneath large flip chips will encourage today’s microelectronic packaging industry to meet the challenges of smaller and denser components.
Hanzhuang Liang, Staff Engineer, PhD, PE
Carlsbad, CA

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