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A wafer-level system integration technology incorporates heterogeneous devices
Keywords: Wafer-level packaging, System integration, Pseudo-SoC
The heterogeneous devices system integration technologies reported are mainly implemented for the monolithic integrated SoC (System on Chip) by applying the advantages of compatible processes. However, it has been impossible to integrate them in the case that each device processes are incompatible and many integration technologies, by applying SiP (System in Package) technology with the interposer substrate, are reported to realize electronics devices. However, using SiP technology, it has not been possible to achieve high integration density comparable to that of monolithic integrated SoC because the interposer substrate occupies a large area in SiP. Accordingly, development of an advanced system integration technology to realizing highly integrated SoC incorporating heterogeneous devices is required. Toshiba is doing research on pseudo-SoC technology incorporating heterogeneous devices (1). The pseudo-SoC is set up to realize one microchip with heterogeneous devices made by using individual processes for epoxy resin, insulating layer and global redistribution layer, respectively. The individual heterogeneous devices (KDG: Known Good Die) are embedded in the epoxy resin to reconfigure the integration wafer. As the insulating layer and redistribution (global) layer are formed by semiconductor wafer process without interposer substrate, the pseudo-SoC enables integration density and signal transmission speed as identical to that of SoC. Also, as the commercial LSI devices and peripheral passive components are able to use for the system integration, the pseudo-SoC enables reduction of time-to-market as identical that of SiP. This paper presents and overview of heterogeneous device integration technologies and then focuses on the pseudo-SoC that overcomes the limitation of system integration and provides the complementary advantages of SiP and SoC with various applications. (1) This work is part of the Fine MEMS Project supported by the New Energy and Industrial Technology Development Organization (NEDO).
Hiroshi Yamada, Senior Research Scientist
Toshiba Corporation, Corporate R&D Center, Electron Devices Laboratory
Kawasaki, Kanagawa

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