Here is the abstract you requested from the nano_2012 technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.
|What's real in 3D ICs and TSVs in today's and tomorrow's microelectronics.|
|Keywords: 3D ICs, TSVs, Silicon Interposers|
|Over the past few years a vast array of products have been implemented in one form or another of 3D packaging. Military and aerospace developed and deployed 3D packaged microelectronics for more than four decades. Their need for more electronics in a smaller volume or with reduced weight overcame the high cost and poor yield of 3D approaches. Today, 3D is alive and well and being used in every high-to-mid-range smart phone and is rapidly becoming the low cost solution for portable microelectronics and increased memory capacity and speed in high-end computing. Todays 3D protfolio include Package-on-Package (PoP, chip stacks using chip-to-chip wire bonds, stacked chips and packages with edge-of-stack connections, stacked embedded chip packages with thru-plastic vias (TPVs)and many other approaches. By far the highest electrical performance and the highest density 3D approach is 3D ICs where two or more chips are interconnected using Thru-Silicon-Vias (TSVs). This paper will detail the various 3D IC approaches, describe where they are or will be used. It will cover 2.5 D vs 3D, TSVs first or TSVs last, chip stacks vs chips on interposers and memory chip stacks vs logic chip stacks.|