Here is the abstract you requested from the nano_2012 technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.
|Package Innovations for Meeting Challenging Requirements|
|Keywords: Packaging, HPC, Nano materials|
|The next generation of computing devices such as microprocessors and FPGAs will place major challenges on packaging technologies. Semiconductor processing, architecture and feature advances will enable significant performance advances in processor speed, integrated functionality and overall processor performance. These in turn drive increasing I/O counts (>10,000), decreasing bump pitch (<150 microns), lower core voltage (<0.85V), higher current loading (>100A), higher power dissipation (>150W), and faster switching times. At the same time, lead-free and RoHS international regulations are putting new restrictions on material selection with the inherent problems associated with lead free bumps and smaller pitch bumps such as susceptibility to electro-migration that packaging fabricators must provide mitigation means. Innovative nano materials can be deployed in several critical packaging areas to meet theses challenges. For example, in high speed device power supply decoupling applications, embedded capacitance layers with nano particles can provide high capacitance with ultra low loop inductance. Nano particle based thermal interface materials have highly desirable properties for high power density device thermal management tasks. Recent experimental results have shown that the nano material based conductive adhesive can be used in Z interconnect structures with excellent joint reliability and low resistivity.|
|How T. Lin, Chief Scientist
Endicott Interconnect Technologies, Inc