Micross

Abstract Preview

Here is the abstract you requested from the nano_2012 technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.

Standards for 3D Stacked Integrated Circuits
Keywords: standards, three-dimensional stacked integrated circuits, silicon wafers
This talk will describe recent activities by SEMATECH’s 3D Enablement Center (3D EC) to accelerate the adoption of three-dimensional stacked integrated circuits (3DS-ICs) by supporting the development of a cohesive set of end-to-end standards at the interfaces between supply chain partners. Support for these activities will be through the leadership of committees developing standards, providing material support to experiments needed to validate metrology for 3DS-ICs, and fostering a community with a public and centralized website to provide easy-to-use links to the standard development organizations (SDOs) involved in standards development for 3DS-ICs. The 3D EC was launched in December 2010 with the mission of enabling industry-wide ecosystem readiness for a cost-effective TSV-based 3D stacked IC solution. Initial activities of the 3D EC are focused on areas identified as highest needs in an industry survey undertaken by SEMATECH in 2010; this survey identified the highest priority needs for heterogeneous stacking, focused on mobile wide IO DRAM. 3DS-ICs are expected to lead to improved density, power consumption, and performance as the first generations enter high volume manufacturing. They also hold promise as enablers of heterogeneous integration in future years. Since many advanced 3DS-IC processes will depend on wafers sourced from multiple fabrication lines (logic, memory, MEMS, optoelectronic), the actual 3D stacking will take place at a third-party provider, such as an Outsourced Test and Assembly (OSAT) entity. Despite the promising potential, a lack of uniform standards has impeded the migration of 3D technologies into mainstream production. In particular, cost-effective high volume 3D integration of ICs from multiple sources will require standards such as data exchange formats, wafer and stack definitions, metrology, and the specification for wide IO DRAM. This talk will focus on the ongoing standardization activities addressing these issues.
Richard A. Allen, NIST Assignee to 3D Enablement Center
SEMATECH
Albany, NY
USA


CORPORATE PREMIER MEMBERS
  • Amkor
  • ASE
  • Canon
  • EMD Performance Materials
  • Honeywell
  • Indium
  • Kester
  • Kyocera America
  • Master Bond
  • Micro Systems Technologies
  • MRSI
  • NGK NTK
  • Palomar
  • Plexus
  • Promex
  • Qualcomm
  • Quik-Pak
  • Raytheon
  • Specialty Coating Systems