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Wafer-Level Parylene Diffusion Barriers for a Self-Referenced CMOS LC Oscillator
Keywords: Parylene, Wafer Level Processing, Moisture Diffusion Barrier
The suitability of a wafer-level fabricated parylene moisture barrier is evaluated for use on a self-referenced and temperature-compensated CMOS frequency generator. Electromagnetic fields fringe from the planar surface of the frequency generator and are modulated when the packaging dielectric properties change, particularly in the presence of moisture. When moisture is introduced into the packaging, the self-resonant frequency of the generator will drift. This work considers the placement of patterned Parylene‐C material over the critical circuit and in the electric field area to form a region of constant dielectric in the presence of dynamic humidity changes. Three wafer-level processes for the patterning and removal of Parylene-C will be discussed: a CMP process and two plasma etch processes using a sacrificial resist layer and a hardmask. The materials used these processes are available as standard BEOL materials. The parylene was patterned onto 8-inch wafers containing devices of dimensions 1 mm by 1mm. The devices were then encapsulated using standard plastic packaging techniques. For evaluation the plastic part was subjected to a long-term moisture diffusion test and the generator output was constantly monitored for frequency modulations. Parts were compared to standard plastic parts and parts with a patterned dielectric sealed with a diffusion barrier. Results indicate that a single layer of Parylene over the device is effective at preventing moisture intrusion, and subsequent dielectric change, over the critical circuit region. Co-author email: Bhusan Gupta (bgupta@idt.com)
Nathaniel Gaskin, Sr. Design Engineer
Integrated Device Technology
Sunyvale, CA
USA


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