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Enhancing Overall System Functionality and Performance with the Right Packaging Solution
Keywords: RF/Microwave Package, Wireles System miniaturization, Systen-in-Package
Remarkable changes are happening to wireless technology through miniaturization, integration and innovation in both integrated circuits (IC) and packaging in order to meet future challenges of greater functionality, higher performance, smaller size, lower cost, and faster time to market. To achieve this objective, SoC and packaging technology must complement each other in order to enhance overall system functionality and performance. Integration of complete systems of RF/analog/digital functions in a single-chip SoC is facing many obstacles due to the system requirements for high capacity memory devices, Duplexer Banks, MEMS, high Q Integrated Passive Devices and other multimedia devices. The market demands that these features be delivered in innovative form factors. In response, 3D packaging is experiencing high growth in new applications by delivering the highest level of silicon integration and area efficiency. To achieve design flexibility and cost objectives, phone designers have turned to stacked die, SiP, PiP, and PoP to solve their RF, logic, passive component, and memory integration challenges. These package integration solutions must pass board level solder joint qualification, wireless device drop test, and all other mechanical rigidity requirements. A new design methodology is needed to partition different segments of the system functionality which isolates them from coupling among different circuit segments of the cell phone system, protects them from EMI interferences and noise susceptibility.
Nozad Karim, VP; Technology and Platform Development/Electrical Engineering
Amkor Technology
Chandler, AZ
USA


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