Here is the abstract you requested from the rf_2012 technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.
|3D Stacked Die SIP Packaging for High Performance Cost Sensitive Applications|
|Keywords: 3D, Packaging, SIP|
|As demand for handheld electronics continues to accelerate, and the need for wireless connectivity grows with it, the need for cost effective high frequency solutions for multi die packaging has been a driver for a variety of TSV and Flip Chip solutions. Moving from single chip SOC solutions to multichip packaging allows the system to be optimally partitioned, avoiding compromises one must make when designing RF/High Frequency blocks and lower speed digital baseband blocks that must be manufactured in the same process. While TSV solutions offer a lot of interconnect electrical advantages, as well as system partitioning flexibility, the high capital cost and manufacturing complexity has made TSV most applicable to a small set of high volume products with high interconnect count that truly benefit after silicon area penalties are accounted for. Vertical Circuits (VCI) has developed a low cost method for multi die packaging that minimizes footprint and provides electrical advantages as a result of utilizing the shortest possible lead lengths, and hence minimizing inductance and other parasitics. The use of a conformal dielectric coating on the edge of stacked die, along with a conformal conductor that is applied as a liquid, and then cured, results in an ultra thin packaging solution with minimal footprint. In addition to simplifying vertical interconnect, die and signal lead shielding can be provided for as well. The technology allows a wide degree of freedom and flexibility in package design, footprint, and die choice, and has been licensed to major high volume OSAT suppliers for volume production. In this talk we will review the process, materials, and methods that have been optimized for this package, look at some typical OEM applications that have benefited from the improved performance and shielding options, and highlight key physical and electrical characteristics of this packaging method.|
|Marc Robinson, Vice President/CTO
Vertical Circuits, Inc.
Scotts Valley, CA