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|A 4H-SiC bipolar technology for high-temperature integrated circuits|
|Keywords: silicon carbide, high temperature, bipolar integrated circuits|
|Silicon Carbide (SiC) is a semiconductor that provides very interesting advantages for high-power and high-temperature applications [Zetterling, C.-M. (2002)] thanks to its wide band-gap, which results in high critical field and low leakage current. The high-temperature operation and the relaxed cooling requirements of SiC devices make it a very promising material for high-temperature applications. For this reason several high-temperature SiC integrated circuits (ICs) have been recently reported. Operation of CMOS and bipolar ICs has been shown in 4H-SiC up to 400 °C [clark, D. J. et al. (2012)][Young, R.A.R. et al.] and up to 355 °C [Singh, S. & Cooper, J. A. (2011)] respectively. Whereas JFET-based digital gates in 6H-SiC have reported operation up to 550 °C [Soong , C.-W. et al. (2012)]. This work reports a SiC bipolar technology capable of 500 °C devices and digital ICs. The starting technology, for which IC operation up to 300 °C has been already demonstrated [Lanni, L. et al. (2012)][Lanni, L. et al. (2012)], is now tested with two different metal stacks for the final metal layer: Ti/TiW/Al and Ti/Pt. It is worth noticing that all interconnects required in the fabricated ICs are realized with just one metal layer. Test devices and circuits were fabricated on 2-inch 4H-SiC wafers with a 6-layer epi-structure (n++/n+/p/n-/n+/p). The bipolar transistor, used for designing the ICs, is 105µm × 162.5 µm wide and has all terminals available on the top side. Isolation between different devices is guaranteed by the additional p-layer in the epi-structure. From the definition of emitter, base and collector mesas to the opening of via holes exactly the same process was performed on all the wafers. After that, some of them were completed by depositing a Ti/TiW/Al (30/70/1000nm) layer, while on others a Ti/Pt (10/400nm) stack was sputtered. Isolated transistors and integrated OR-NOR gates have been characterized up to 300 °C for both the metal stacks. In both cases the gates, operated on -15V supply voltage, show stable noise margins about 1V in all the temperature range; while transistor current gains decrease of about 50% when the temperature rises from 27 °C up to 300 °C. At 27 °C the highest measured gains are of 74 and 52 (VBC = 0V) for samples with Al and Pt metallization respectively. In particular for the Al metallization, one transistor and one OR-NOR gate have been successfully tested up to 500 °C. At this temperature a transistor current gain as high as 35 has been measured, and a stable operation of the OR-NOR gate has been observed. In particular, the gate noise margins do not degrade when the temperature rises and are about 1V from 27 °C up to 500 °C. Further characterization of test structures, transistors and circuits will be performed up to 500 °C, for both the metallization systems. In particular, contact chains and integrated resistors will be tested with suitable current densities up to 500 °C.|
|Luigia Lanni, PhD student
KTH Royal Institute of Technology