Device Packaging 2019

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Integrated GaN Power Modules
Keywords: Gallium Nitride, Density, Temperature
In this paper the authors describe GaN (Gallium Nitride) power switching transistors that use copper post and substrate via interconnect techniques. These transistors can be matrixed to allow a parallel array of the devices to provide very low on-resistance and high operating voltages. The basic building block is a 2mm x 2mm die that provides 1200V / 20A operation with an on-resistance of 180 mOhms. A 3x4 matrix array of these transistors provides for example, 1200V / 240A operation with an on-resistance of less than 15 mOhms. The overall device size is 6mm x 8mm. This high current density and low on resistance is achieved by using a unique castellated topology. This provides short fingers that are not required to carry high current. No high current tracks are provided on-chip. On-chip metal is typically only 3 microns thick. The die has 12 copper posts on the source islands and 12 through wafer vias from the device islands that carry the current to the external metal interconnect which can be made 25 to 50 microns thick. This technique therefore eliminates electromigration issues and allows for a large number of die to be connected in parallel. The devices can therefore be completely enclosed within two copper plates. All the drains and sources of each of the dies are connected together. The gates are strapped together with a deposited copper-on-polyimide track. The paper provides a thermal analysis of the assembly. The primary objective of the design is to keep the surface temperature of the GaN transistors below 225°C.
John Roberts, CTO
GaN Systems Inc.
Ottawa, ON

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