Device Packaging 2019

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A 250C ASIC technology
Keywords: ASIC, 250C, SOI
Tekmos has developed a 250C ASIC technology that uses the X-Fab XI10 SOI process. A gate array architecture was chosen to allow reduced mask costs and quicker manufacturing cycle times. The design of the technology includes first determining the optimum routing grid, and then designing of the basic gate array transistors. The “A” style transistor was chosen over the “H” style to create stronger transistors. The choice of the transistor in turn sets the characteristics of the basic “block” that is used in the gate array architecture. Another factor in the block design is the requirement for a pre-determined source with “A” transistors. This prevents the use of shared diffusions that are used in most gate array architectures, and resulted in a different block layout. The pre-determined sources also required a change to the logic cell library. Since the basic transmission gate found in most flop designs cannot be used, alternative logic architectures were developed. By implementing the SOI specific library into our standard logic library, we are able to mask the SOI peculiarities from the end designer. The 250C ASIC technology was demonstrated in a FPGA conversion, in which a design in an Actel MX series FPGA was re-implemented in the 250C ASIC technology. We used a standard FPGA design conversion flow, and the only issues were related to the speed and voltage differences between the FPGA and the 1.0u ASIC. These were addressed through critical path analysis and some slight circuit modifications. The temperature derating for 250C was significant, but we still retained enough margin to allow the circuit to work. Parts were made, and worked as expected at 250C. The life testing results at 250C have been satisfactory. On an experimental basis, parts were evaluated at temperatures of up to 305C without failure.
Lynn Reed, President
Austin, TX

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