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Thermally and Electrically Enhanced Wirebond BGA
Keywords: Thermal enhancement, Heat Spreader, Electrical enhancement
Next-generation processors continue to demand more thermal and electrical performance from the package. Frequently devices are designed into Flip Chip (FC) packages where the predecessor generation was in Wire Bond (WB) since FC typically provides superior thermal dissipation and lower package electrical parasitics than WB. However, FC packages usually have higher cost for mid-range IO (500-800). An Enhanced WB BGA package has been designed with improved thermal and electrical performance compared to the industry standard TEPBGA-2 (thermally enhanced PBGA type 2). The molded-in heat spreader used in the TEPBGA-2 results in a 500um barrier of mold compound between the die and heatspreader. This barrier is a major impediment to heat flow out of the package. By contrast, the Enhanced WB package uses post-mold attachment of a heat spreader which is adhesively bonded to the mold cap and thermally coupled to the die using a 40um TIM (thermal interface material). Improvements to substrate design rules and the die attach process allowed the Enhanced WB design to shorten bond wires by 40%, which enabled the electrical performance improvements. Package thermal resistance, Theta-Ja, was verified by simulation and measurement to be 3C°/W lower than TEPBGA-2, which would allow dissipation of up to 15W in some end-use applications, approximately 2x the performance of TEPBGA-2. DDR set-up and hold time showed 30ps improvement by both simulation and measurement. Cost is estimated to be at parity with the TEPBGA-2 package now in production. This paper will present the package design, thermal and electrical simulation and measurement results. JEDEC MSL and temperature cycle stress test data will also be shown.
Burton Carpenter, Senior Member Technical Staff
Freescale Semiconductor, Inc
Austin, TX
USA


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