Here is the abstract you requested from the IMAPS_2013 technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.
|DEVELOPMENT OF AN ULTRA THIN DIE-TO-WAFER FLIP CHIP STACKING PROCESS FOR 2.5D INTEGRATION|
|Keywords: ultra-thin die, flip chip stacking, 3D|
|3D integration relying on novel vertical interconnection technologies opens the gate to powerful microelectronic systems in ultra-thin packages answering the demand of the mobile market. Among these, die-to-wafer stacking is a key enabling technology for 2.5D as well as for 3D with technological challenges driven by in one hand the increase of the die surface and the number of I/Os and on the other hand the reduction of the vertical dimensions. In our integration scheme we have achieved flip chip stacking (or Face to Face) of 35 µm ultra-thin dies with low stand-off (< 15 µm) copper micro-pillars and tin-silver-copper solders (SAC). Copper µpillars technology is challenging with this very low profile stacking since the current flip chip process is no longer adapted to this geometry and that the die flatness tolerance become very critical to obtain a high soldering yield. Ultra-thin dies are prepared using dicing before grinding (DBG) technique. After DBG, plasma stress release process is applied to the backside of the singulated chips. Process improvements have been achieved on the copper pillar fabrication itself with several metallurgy stacks configurations. Furthermore, innovative technologies have been deployed on the pick and place and collective soldering processes. Intermetallic formation during reflow process is achieved through transient liquid phase (TLP) reaction leading to thorough consumption of the tin layer and to the formation of Cu6Sn5 and Cu3Sn compounds. Capillary underfill is finally successfully applied in the narrow die-to-wafer gap by jetting technique. After optimization, electrical tests show a very high yield close to 100% over a representative number of fully populated wafers. Reliability tests have also been carried out at wafer level exhibiting no significant resistance increase or yield loss over 1000 thermal cycles between -40 and +125°C.|
|Gabriel PARES, Project Leader