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Flip-chip packages with periphery Cu pillar bumps as wirebond replacement—Design, Modeling & Characterization
Keywords: Copper pillar, flip chip packages, signal integrity and power integrity
Package design and interconnect technology significantly affect IC and package electrical performance. This paper presents a novel IC packaging solution with periphery Cu pillar bumps for low cost, high density and high performance FPGA applications. Wire bonding has traditionally been dominant over this package space, and still maintains lots of tractions for high volume production. Current wirebond technology is capable of 60 ~ 80 um pitch with 2 ~ 3 tiers of bond pads at die periphery regions. Wirebond loops requires additional 100~ 200um Z-height and 300um minimum X/Y spacing in order to connect die with substrates. IO density of the wirebond packages is limited by wirebond loop connections. And for the same reason, another challenge for wirebond technology is high wire inductance, which can limit signal bandwidth. Also due to the high wire resistance, more wires need to be allocated for power and ground connections. As a rule of thumb, 30~50% wires can be dedicated to power and ground in order to meet the DCR requirements. Migration from wirebond to Cu pillar technology is mainly driven by IO limited design and small form factor. Cu pillar bumps also offer significantly higher current carry capacity and better electrical performance compared to wire bonds. With a new technology, there are also design challenges in order to optimize IO and PDN performance for IO density and cost efficiency. This paper will address these challenges through design, modeling and characterization of an 11x11mm2 flip chip BGA package. Cu pillar bumps in the form of periphery arrays are implemented to achieve high IO breakout on low cost substrates. Die to package size ratio is roughly 1:1.4. Total pin count is 301 with 0.5mm BGA ball pitch. Flip-chip packages with Cu pillar bumps eliminate two primary limits of wirebonds—it reduces interconnect inductance and provides more bumps for power distribution. Link simulation data shows Cu pillar bump has very low impacts on 5Gbps channel insertion loss and return loss, and has very consistent performance for all channels across the package. Benefit for PDN is Cu bump low resistance. Flip-chip packages also allow more power bumps extended to core regions and more even power distribution to improve die and package PDN performance. Full paper will explain in details on leveraging Cu pillar technology to improve package performance on high speed channels and power distribution. Channel insertion loss, jitter, timing, PDN impedance and noise analysis will be presented with hardware correlation to validate system performance.
Zhe Li, MTS
Altera Corporation
San Jose, California
USA


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