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Thermally Activated Bumping Process of Sn3.0Ag0.5Cu Solder for Low-Cost Interposer
Keywords: Solder-on--pad, Maskless, fine-pitch bumping material and process, Cu pillar
Nowadays, the interposer technology is being highlighted because it can implement the hybrid integration technology on the interposer using the advanced flip chip bonding technology for the high-end devices such as FPGA, CPU and GPU. However, Its commercial use has been slowing due to its high-cost. For example, the cost for a silicon interposer wafer is reported as two times higher than a 300-mm 28nm wafer at a foundry. The major cost of a silicon interposer is considered contributed from the TSV process, backside process, and stacking process. Among them, CuSn bumping process in the backside process costs higher than the stacking process. Currently, the electroplating process is mainly used to form a CuSn bump array on the Si interposer. There are many other candidate technologies for the bumping process such as solder jetting, Controlled Collapse Chip Connection New Process (C4NP), micro-ball placement and so on. However, these are not considered proper for a low-cost interposer. In this paper, maskless, fine-pitch, low-volume, and Sn3.0Ag0.5 (SAC305) solder-on-pad (SoP) material and process are proposed for a low-cost silicon or glass interposer. Its cost advantage comes from the use of the well-known infrastructures such as a maskless screen printing process. The ternary, lead-free solder bumping can be possible because of the use of the commercial solder powder. A novel material, named as solder bump maker (SBM) was reported previously for this purpose. The SBM material and bumping process using the SBM were designed carefully, especially for the formation of the fine-pitch and low-volume solder bump array. We applied the solder powder with a diameter distribution according to type 7 in the IPC Std. J-STD-005 to make the SBM. We developed the bumping process using the SBM, suitable to obtain fine-pitch and low-volume solder bump array. The process features two high-temperature steps; the first step is for the aggregation of the solder powder on the pads on a substrate and the second for the reflow process to form a solder bump array on the substrate. The peak temperature of the first heating step is below the melting point of the solder powder, so that only the gravity forces, surface tensions and diffusion phenomena control the aggregation of the solder powder on the pads. As test vehicles, daisy chain chips with Cu pillar with and without solder cap with pitch of 60μm and silicon substrates were fabricated. The low-volume SoP array was, successfully, formed on the metal pads on the substrate using the SBM and process as mentioned above. After the flip bonding process of these test vehicles, the comparison was made between the test vehicles with and without solder cap. From the results, it was concluded that the solder bump array formed using the SBM can give enough volume to the flip chip interconnections so that the solder cap on the Cu pillar is not necessary and, at the same time, the solder volume is low enough to prevent the solder bridge during the flip chip bonding process.
Kwang-Seong Choi, Principal research engineer
ETRI
Daejeon, Chungnam
Korea


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