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Chip Design of an 1 V RF Receiver Front-End for 5.8-GHz DSRC Applications
Keywords: receiverfront-end, DSRC, low voltage
An 1 V RF receiver front-end applying in 5.8 GHz DSRC (Dedicated Short Range Communication) systems is presented in this paper. The proposed chip includes a current-reused LNA, a folded Giber cell mixer, a Colpitts VCO, and an IF Gm-C bandpass filter. The measured results of the chip show an input return loss of 20 dB, a conversion gain of 29 dB, a double-side band (DSB) noise figure (NF) of 5 dB, and a third-order intercept point (IIP3) of -24.4 dBm. The on-chip oscillator shows the measured tuning range of 5.17-5.98 GHz and phase noise of -118.5 dBc/Hz at 1 MHz offset from the 5.8 GHz carrier. The proposed receiver front-end is fabricated in a 0.18 μm CMOS process with a power consumption of 27.6 mW from a 1 V supply voltage. The chip area including PADs is 1.75 x 1.2 mm2.
Wen Cheng Lai,
National Taiwan University of Science and Technology
Taipei, Taiwan

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