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Stacking of known good rebuilt wafers for high speed memory and SiP
Keywords: System-In-Package, DDR3, Medical
Based on Wire free Die on Die disruptive technology (WDoDTM), high density memories can be manufactured in a small factor package size. Stacking known good rebuilt wafers allows high yields while integrating high performance devices. Consumer memory market is not a 3D-Plus commercial target, however, extended temperature range or wide bus memories for industrial and military applications are clearly rising up a lot of interest. Moreover, such a product demonstrates 3D-Plus know-how in the three dimensional integration required by the industrial market (medical, defense etc). Wafer processing is done at Nanium with their in-house e-WLB technology and a specific redistribution layer (RDL) is designed to match with 3D-Plus bus metal edge interconnect technology. 300 mm rebuilt wafers are processed and thinned down to 200 µm before stacking and gluing. The wafer alignment is within ±5 µm allowing small lateral pitches demonstrating WDoD versatility with denser I/Os products such as FPGA. Final package sizes are 8.5x11x1.0 mm and 8.5x11x1.4 mm for the dual and quad die configurations respectively. The qualification of the WDoD has been made with DDR3 dies (8 bits 1Gb) with a JEDEC compatible . Electrical test is performed at Nanium at 2 frequencies and 3 temperatures 533 MHz and 667 MHz and -10°C, 25°C and 125°C, respectively. Retention, timings and leakages are characterized to fully define component behavior. Known good die sourcing is key as one failing or poorly performing die jeopardize the final component. Nevertheless, dual die and quad die DDR3 memories exhibit outstanding performance and show the path to highly integrated System in Package (SiP). Two SiP applications for each domain will be presented: - Medical application with a micro pacemaker of 0,5 cm3, - Defense and industrial application with a calculation node based on bare die FPGA, DDR3 and PROM memories and a special very low inductance decoupling capacitors level.
Dr Pascal COUDERC, R&d manager

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