Here is the abstract you requested from the IMAPS_2013 technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.
|DIMM-in-a-PACKAGE (DIAP) signal integrity for high-performance on-board memory applications|
|Keywords: QFD, DIMM-in-a-Package, signal integrity|
|The recent explosion of thin notebooks and tablets has challenged the IC packaging industry to come up with new solutions of DRAM integration to motherboard. Beyond traditional SO-DIMMs, innovative memory solutions should perform well at high speed (1600 Mt/s) with much reduced footprint and Z-height, while leveraging current manufacturing infrastructure for lower cost and also enabling simpler and cheaper motherboard design. To accomplish all the goals stated above for high-performance on-board memory applications, we showed a new DIMM-in-a-Package (DIAP) technology. This 22.5x17.5x1.2mm quad-die face-down (QFD) part has four standard center bond DDR3L dies (each x16) face-down, which are wire-bonded to the bottom layer of the 407-ball BGA package. This judiciously designed package places data nets at the peripheral and command/control/address nets in the middle of the BGA. As such, motherboard design and layout were substantially simplified to allow the use of low-cost non-HDI Type 3 board for signal integrity performance comparable to expensive HDI boards. The QFD’s ball assignment could accommodate future memory density expansion and different memory type (e.g. LPDDR3, DDR4); it also enables dual-rank operations in each channel when double-sided assembly is used. We successfully demonstrated in production build that 1GB x64 DDR3L QFD with data rate of 1600 Mt/s can be achieved on a Type 3 motherboard for the Intel Haswell mobile platform in dual-channel dual-rank operation. A balanced-T Command/Address topology between the processor and the memory was implemented in a DELL XPS 12 Ultrabook. Channel simulations including chip, package and board were performed. We also conducted cross-talk analysis up to 9 aggressors to take into account the timing impact from the dense routing inside QFD. Layout optimization techniques for best signal integrity, such as trace length matching and stub length minimization, were discussed in detail and applied to both package and motherboard design. Lastly, we also presented and discussed DIAPs currently under development of STAR and Fly-by memory bus topologies for even higher data rate up to 2400 Mt/s using the same QFD technology. Our results and analysis demonstrated DIAP using wirebond-based QFD technology as a viable candidate for the compact, low-cost, high-performance on-board memory solution. We have identified several key aspects of DIAP architecture design and physical layout that are strongly impacting the SI of QFD parts at rate >1600 Mt/s and that could be optimized for DDR4 operations. QFD DIAP can become an attractive low-cost, high-performance option for many OEMs and ODMs in various mobile, personal and network computing platforms.|
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