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Package Technology Selection of 28nm High Power FPGA with Pb-Free Bumps: Flip Chip Molded BGA Versus Traditional Bare Die Package
Keywords: Pb-Free Bumps, Flip chip, BGA
Selecting the optimal flip-chip package technology for the next generation 28nm FPGA is critical not only to meet reliability benchmarks for Pb-free bumps, but also in meeting the field-use environment requirements for high power devices. Component level reliability testing was conducted on three separate package types: Bare die flip chip BGA (FCBGA), flip chip molded BGA (FCMBGA) with capillary underfill, and FCMBGA with molded underfill. Testing was conducted independently at two separate facilities. Testing included moisture resistance testing (JESD22-A102D Condition Level C), temperature cycle (JESD22-A104 Condition Level B), 1000hrs bake and hybrid test combining 100 hours of unbiased hast with temperature cycling. Reliability monitoring was conducted through multiple means including electrical testing for circuit continuity, CSAM imaging at frequent read points to monitor silicon integrity and underfill adhesion performance, cross-sections for the inspection of bump crack propagation, and FIB analysis of the UBM structure after test completion. In addition to reliability testing of three flip chip BGA platforms, other usage factors were considered. These included package specific design rule flexibility and future generation packaging requirements. The results of the evaluation demonstrated that bump integrity remained strong for all three package types – showing no cracks after 1,500 temperature cycles and 1000hrs of bake. The performance of both molded flip chip packages was equivalent and each was better than the bare die. Ultimately, the FCMBGA with molded underfill was selected based on design rule flexibility for passive components as well as robustness on component test handling compared to the other two capillary underfill package options.
Corey Reichman, Staff Engineer
Amkor Technology
Chandler, AZ
USA


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