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Performance and Process Comparison between Glass and Si Interposer for 3D-IC Integration
Keywords: glass interposer, Si interposer, 3D IC integration
Through silicon via (TSV) and through glass via (TGV) interposer fabrication processes are critical techniques in 3D-IC integration, providing the short interconnection among different stacked chips and substrate. Nowadays, silicon is a mature material in semiconductor technology, but glass, a dielectric material, provides an attractive option due to its intrinsic characteristics for the advantages of electrical isolation, better RF performance, better feasibility with CTE and most importantly low cost solution. In this investigation, the glass interposer by using TSV industry equipment and tooling was evaluated and developed, and has been compared in complete processes and electrical characteristics with silicon interposer. In order to simulate and measure the electrical performance, patterned interposer wafer with 30μm diameter and 100μm depth Cu-filled TSVs are designed and prepared in advance. Because electrical performance is a major concern and decided mainly by the substrate. We designed some transmission lines and through vias in Si and glass materials for wideband transmission loss comparison. According to the measurements and analyses, the results reveal that transmission loss of CPW on glass interposer is about 0.3dB at the frequency of 10GHz, brilliantly outstands 2dB loss on silicon interposer. Simulation results are also compared to measurement in detail and the maximum deviation is below 4%. In addition, the via forming of glass interposer eliminate isolation layer, which leads to the merit of less parasitic effects. Therefore, we propose a guideline to model TSV and TGV in terms of RLGC for the ease of verification in system level applications. As for the chip stack modules with glass interposer were assembled to evaluate their electrical/thermal performances. Assembly process of the chip stack was developed and reliability performance was also estimated. Temperature cycling test (TCT) under the test condition of -55°C~125° was performed on the chip stacking module with the glass interposer to assess the reliability responses of the heterogeneous 3DIC SiP. In this investigation, the performances of the chip stack with glass interposer characterized by the considerations of electrical, thermal and assembly were presented.
Chun-Hsien Chien, project manager
Industrial Technology Research Institute
Chutung, Hsinchu
Taiwan


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