Abstract Preview

Here is the abstract you requested from the IMAPS_2013 technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.

Accurate finite element analysis of embedded wafer level packaging by thermomechanical characterization of materials and ICs piezoresistive stress sensors
Keywords: Embedded wafer level packaging , Thermomechanical characterization, Finite element analysis
Embedded wafer level packaging (eWLP) is an attractive solution for producing heterogeneous and compact electronic packages. Thermomechanical behavior of such heterogeneous system is the cause of both fabrication and reliability issues, especially when 3D integration of organic packages is preferred. In the present work, the thermomechanical behavior of ultra-thin eWLP system is performed by finite element analysis. The organic package made on 8 inches substrate is composed of 70 µm thick silicon dies that are embedded in an epoxy materials with a filler size of 25 µm. Both pick and place process and temporary carrier flip-flop has been optimized to create the 100 µm thick final organic package. Numerical modeling has been conducted according to material thermomechanical behavior. The static and dynamic thermomechanical properties of both the viscoelastic epoxy mold and the thermorelease tape have been conducted. In a first step, minimization of both bow and warp of the organic package at different step of the fabrication process have been analyzed. Two glass carriers have been selected according to the density of silicon dies that are embedded in the epoxy mold. In parallel, infra-red interferometric characterization of the bow and the warp are shown to be in good agreement with numerical results. In a second step, the residual stress generated in each silicon die that is embedded in the epoxy at different location has been studied. Numerical analysis and electrical measurement extracted from the drift mobility of embedded transistors shows that the mechanical stress is in the order of 20 MPa. This low value of stress is sought for the fabrication of embedded integrated circuits (ICs) that included microprocessor and memory within the same package. Further design rules have been conducted using finite elements analysis especially for the 3D integration of organic packages.
Sinh Vuhoang, Research Engineer
Ecole Nationale Supérieure des Mines de Saint-Étienne (ENSM-SE), Centre of microelectronics Provence
Gardanne, FRANCE

  • Amkor
  • ASE
  • Canon
  • Corning
  • EMD Performance Materials
  • Honeywell
  • Indium
  • Kester
  • Kyocera America
  • Master Bond
  • Micro Systems Technologies
  • MRSI
  • Palomar
  • Promex
  • Qualcomm
  • Quik-Pak
  • Raytheon
  • Rochester Electronics
  • Specialty Coating Systems
  • Spectrum Semiconductor Materials
  • Technic