Here is the abstract you requested from the IMAPS_2013 technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.
|Advanced Warpage Characterization for FOWLP|
|Keywords: FOWLP, Warpage, Characterization|
|Current standards for silicon wafers shape characterization use simple metrics. Warpage and bow are computed as the mean surface wafer heights range or the mean surface wafer center height, respectively. These metrics are valid for silicon wafers because of their homogenous and linear thermomechanical properties. In fan-out wafer level package (FO-WLP), embedded Wafer Level Ball Grid Array in specific (eWLB), the use of epoxy mold compound that works both as the physical carrier of the dies and as the base of second level connections has a major impact on the overall macroscopic behavior of the wafer, inducing shapes that do not follow a simple bended or bowed wafer, impacting wafer processability. Warped wafers can affect device performance, reliability, and linewidth control in various processing steps. Early detection will minimize cost and processing time. In our research, we present a solution for wafer characterization in FO-WLP by increasing the information vector that one obtains from standard automated non-contact scanning equipment. For this, we defined wafer shape and wafer ratio as the two new metrics besides warpage, creating a three dimensional vector that can be used to compare and evaluate wafers in high volume production or even single wafer analysis. This is a major improvement over previously used approaches, in which only the average warpage is considered. These metrics were determined by the developed numeric algorithm and their validity was demonstrated through the use of different production conditions, wafer constructions and production monitoring. The proposed approach requires no extra processing steps and time, as compared to conventional off-line methods. Experimental results demonstrate its feasibility and repeatability. This methodology was successfully used in the field and proved to be of high value when evaluating wafer geometrical requirements for both product development and process monitoring.|
|Jorge Teixeira, Integrator backend technology
Vila do Conde, Porto