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Solder Joint Reliability Study of Wafer Level Packages on Flexible Board
Keywords: Wafer Level Package, flex board, parametric modeling
Applications of Wafer Level Packages (WLPs) have shown tremendous growth in the rapid developing smartphones and other portable electronic devices. The technology trends lead to smaller chip size, low cost, and more integrated functions, but also face higher reliability requirements due to the reduced number of solder joints and smaller bump size and height. New working environments such as flexible phone board and conformal coating also bring up new thermo-mechanical reliability challenges. Based on 3D finite element modeling, the current studies focus on solder joint reliability of WLPs and compare its temperature cycling performance on traditional PCB and on flex board. Conformal coated WLP on flex board is also studied and compared with the underfilled WLP. The parametric studies were carried out in the ANSYS modeling environment and all models were created by APDL (ANSYS Parametric Design Language) scripts. All simulations start from the stress free status at solder reflow temperature and were subjected to thermal cyclic load between -40 and +125oC with one hour cycle time. Creep strain was considered for solder alloys and kinematic plastic hardening was considered for other elastic-plastic materials. The fatigue life of solder joint is estimated by the modified Coffin-Manson equation and was compared with available thermal cycling test data. The results obtained from the studies are useful as a design guideline for the enhancement of board level WLP reliability. Keywords: Wafer Level Package, flex board, conformal coating, finite element modeling, parametric modeling, thermal fatigue life, microelectronic package
Gary Gu,
RF Micro Devices Inc
Greensboro, NC

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