Here is the abstract you requested from the IMAPS_2013 technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.
|A Wide I/O Memory-on-Logic Product Prototype Enabled by Through Silicon Stacking Technology|
|Keywords: Through Silicon Stacking, Memory on Logic, 3DIC|
|In recent years, Through Silicon Stacking (TSS) has garnered much attention as a candidate technology to break through the “memory wall” between a processor/digital die and off-chip system memory. Using Through Silicon Vias (TSVs) to electrically connect the frontside circuits of a digital silicon die to its backside, and bonding a wide I/O memory die to the backside of this digital die promises significantly reduced interconnect parasitics and markedly improved memory access bandwidth. Such a digital-die-to-memory-die back-to-face configuration continues to facilitate the strong drive power demanded by the digital die directly through the package substrate. In this paper, we report on a 28 nm High-K metal gate (HKMG) product prototype assembled back-to-face with a 4Gb 3x nm wide I/O DRAM chip using TSS technology in an integrated fabless supply chain . The digital chip interfaces to the wide I/O memory chip using close to 1200 interconnects that are enabled by micro-bump joints with pitch as small as 40um. This micro-bump mediated interface connects to the frontside of the digital chip using TSVs with sub-10um diameter and >8:1 aspect ratio fabricated using a via-mid integration processed concomitantly with the digital die frontside circuits. Our data shows high continuity yields and good signal integrity through the die-to-die interconnects. We show that, while the effect of TSVs on transistors is well-understood , with appropriate chip floor-planning, it is possible to obviate or account for these effects, and re-use 2D circuit IP in a 3D product with minimal die size growth. Moreover, our analyses show, successful integration of TSS-enabling features into the 28nm HKMG die leads to yields comparable to a die without these features. A 3D assembly process discussed elsewhere  allows for a compact form-factor package with <1mm thickness. We present the impact of this assembly process to Wide I/O DRAM performance as well as digital IP performance. Functional integration of the wide I/O memory via a memory buffer on the digital chip allows for memory access rates as high as 200 Mhz. A DRAM BIST interface on the digital chip will be used to test the memory through the wide I/O interface between the two chips. As part of an integrated product solution, we include a test methodology with test stages distributed throughout the integration flow which allow for selection of known good die to minimize assembly yield loss. For the first time, micro-probing of the wide I/O micro-bump interface to confirm through-Si interconnect integrity is reported.|
Qualcomm Technologies, Inc.
San Diego, CA