Here is the abstract you requested from the IMAPS_2013 technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.
|Through Silicon Via (TSV) Arrays for High Frequency Signal Transmission in 3D Integrated Circuits|
|Keywords: TSV, high frequency, signal integrity|
|Through silicon vias (TSVs) enable the 3-dimensional integration of integrated circuits which have the potential to reduce the power consumption, interconnect length and overall communication latency that are currently limiting the performance of 2D ICs. Current system-in-package technology requires multi-functional dies (e.g. logic, memory, analog, RF MEMS, etc…) stacked together using TSVs to enable various types of signal and power transmission including DC, analog, and RF. High frequency signal transmission through silicon substrates is critical for 3D heterogeneous integration yet remains a technological challenge. This paper presents fabrication, testing, and modeling of high-frequency interconnects based on through-silicon vias (TSVs) and coplanar waveguides (CPWs) for stacked integrated circuits (3D ICs). Three distinct signal/ground TSV configurations were investigated with respect to high-bandwidth signal transmission between stacked IC layers. For experimental characterization of the broad-band signal transmission behavior of our proposed RF TSV structures, we properly designed and fabricated test structures that contain two sets of signal/ground TSV arrays connected via a back-side coplanar waveguide (CPW). High aspect ratio (5 um diameter by 50 um length) Cu TSVs were fabricated using a ‘via-middle’ approach. The 3D test structure incorporated necessary RF calibration structures and signal/ground probe pads to implement NIST’s thru reflect line (TRL) calibration method. Scattering parameter measurements of fabricated TSV structures for frequencies from 100MHz to 50GHz shows low insertion loss (S21 less than -1dB up to 50GHz) and return loss (S11 lower than -15dB). These results indicate that these vertical interconnect structures exhibit good performance for high speed signal transmission. Interestingly, the experiment results show that TSV array configurations incorporating multiple (4 or 6) ground TSVs do not provide better signal transmission efficiency compared to TSV arrays with two ground TSVs. Finite element method (FEM) simulation of the high-frequency signal transmission was carried out for comparison with experimental measurement results. Modeled transmission and reflection coefficients from TSV+CPW test structures show good agreement with experimental data. The simulated electric field shows the beneficial impact of ground TSVs for electric confinement in the semiconducting silicon substrate. On the other hand, detailed investigation on capacitance and impedance difference of all configurations indicates that multiple ground TSVs can introduce excessive coupling capacitance and exacerbate the impedance mismatch so as to degrade the high frequency signal propagation. The superior behavior of the 1-signal, 2-ground TSV array results from an optimum balance of impedance matching and ground-shielding effects. These results are confirmed by the modeling and provide useful guidance for 3D RF interconnect fabrication and design. We also investigated several factors that impact the TSV signal transmission including via diameter, G/S TSV pitch and oxide liner thickness for insulating the TSV metal from silicon substrate. The comparison of these fabrication process variables and their impact on signal transmission constitutes a useful study for deployment of TSVs for RF and mixed signal systems.|
College of Nanoscale Science and Engineering, University at Albany