Here is the abstract you requested from the IMAPS_2013 technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.
|1000+ IO Package on Package Solution for wide IO applications|
|Keywords: Package on Package (PoP), wide I/O , High Bandwidth|
|Mobile computing devices has seen an explosive growth in last few years and the new generation of smart phones is rapidly evolving to achieve PC level performance. This requires a high performance processor but still at low power since power dissipation is critical to these portable systems that are expected to have a battery life of more than 16 hours. The devices must support a wide range of power hungry applications including HD gaming and video streaming, high resolution cameras, larger displays, etc. This has pushed the transition from single to multi-core processors and dramatically increased the need for multiple memory channels, the channel bandwidth and the amount of memory accessible to each core. To achieve higher memory bandwidth, either the speed, the number interconnects or both must increase. But the low power requirements of the mobile applications may rule out the option of high speed signaling between the memory and the logic. Therefore, significantly increasing the number of interconnects may be a more viable option which would also allow to lower the clock speed and reduce power consumption. The existing Package-on-Package (PoP) solutions are limited by the number of interconnects they provide and their aspect ratios. The conventional PoP stack with solder balls has a serious pitch limitation below 400um. The through mold via interconnects may reduce the pitch to 300um, but this technology is believed to reach a limitation below 300 um. Other approaches including the use of PCB interposers between the logic and the memory face similar challenges and are cumbersome in the assembly process and expensive. Through Silicon Via stacking is expected to be the ideal solution to achieve the ultimate high bandwidth, but the technology must overcome the challenges in process, infrastructure, yield, reliability, supply chain and cost. Bond Via Array (BVA) technology addresses all of these issues while enabling high bandwidth PoP stacking of more than 1000 high aspect ratio interconnects at less than 200um within the standard package footprint . BVA is a cost effective, ultra-fine pitch, high density PoP stacking solution that will assist in driving high logic-memory bandwidth applications with standard assembly equipment and processes. This is achieved by encapsulating the logic package after forming free-standing wire bonds along the periphery of its substrate. The wire protrusions formed above the mold cap at the top of the package are later attached to the BGA at the bottom of the memory package in a standard reflow operation. In this work, we will demonstrate a BVA test vehicle with 1016 PoP interconnects at 240um pitch within a standard 14mm x 14mm package foot print. The critical technological challenges we overcame to fabricate the prototypes along with the detailed reliability performance describing the temperature cycling, high temperature storage, autoclave and drop testing will be discussed. Finite element analysis modeling used to optimize the package structure along with the simulations to describe the electrical performance of the package will also be presented.|
|Rajesh Katkar, Sr. Manager, Discovery, Reliability and Failure Analysis
San Jose, CA