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Keywords: Scallop Free, conductor loss, Low-K
The advanced high-density packaging methods of 2 D, 2.5 D and 3 D are enabling technologies to establish of social infrastructure, which can sensing and being security for huge information content. The wide i/o device using TSV is an enabling technology to achieve high-speed mobile communication in smart-phone and tablet-PC. On the other hand, the development of new memory "HBM (High Bandwidth Memory)" for graphics and high performance computers is also accelerates [1,2]. It is thought that a method of 2.5 D becomes main-stream in that 3D SiP and SoC packaging. Because the Si or glass interposer packaging technologies will solved any issue of thermal, cost and supply-chain. However, there are some issues. Specially, manufacturing flow about take measures against loss of interconnect factors has never been proposed. In this paper, that focuses on reduction of interconnect-loss points, and discus about interface control and materials. General Si via structure (side-wall roughness and dielectric liner material) cannot ignore a "conductor loss" in the TSV structure. For example, the surface roughness on TSV sidewall will affect the signal in a high frequency. As for the deep etching technology of the silicon, the cycled etching method (Bosch method) of repetitious deposit and etching is generally. On the other hand, the sidewall roughness that called "Scallop" is accompanied. It can control this roughness weather extremely small by cycle fast method [3]. In addition, high etching rate of Si is indispensable because general Si interposer is huge with diameter 10 - 30um, aspect ratio around ten. It is hard to avoid the "Scallops" value of 100nm to secure constant etching rate by cycled method. As definitions, R(f) is conductor loss,  is resistivity of conductor skin effect,  is dielectric constant. Generally,  is proportional to R(f) * e. The 100nm levels of surface-roughness leads to enough conductor losses when it considers skin-effect from this equation. Therefore, it is important to form the smooth-surface of TSV's sidewall to reduce a conductor loss. "Scallops Free Etching" technology has developed using by novel high-density ICP (or NLD) plasma for the Si etching [4]. Which plasma is able to get the smooth sidewall (less than 50nm) etching of TSVs in spite of high Si etching rate. Next, the wiring-delay by the dielectric constants of the liner film is important problem. SiO2 film is adopted generally in TSVs, but is fatal to the high frequency device of the GHz band. Therefore, kind of polymer film is introduced as a low dielectric constant and low dielectric loss for a high frequency band. A novel vapor deposition polymerization system for TSV and an example of the film deposition on the fine Si pattern. A polymer film is polyurea. The dielectric constant is about 3. And, there are several advantages about this film. First, this process can deposit on the narrow space, and introduced monomers are harmless to humans in this process. And next, the film deposition temperature is low below 100 degrees. And, the film stress is also quite small. As a result, solution of Si interposer fabrication for next-generation high frequencies to the reduction of the conductor loss and wiring-delay using by the smooth etching "Scallop Free Etching" and the novel polymer film "polyuria" dielectric liner is provided.
Yasuhiro Morikawa, Institute of Semiconductor and Electronics Technologies
Susono, Shizuoka

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